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for more information www.linear.com/lt8613 1 typical a pplica t ion fea t ures descrip t ion 42v, 6a synchronous step-down regulator with curr ent sense and 3a quiescent curr ent the lt ? 8613 is a compact, high efficiency, high speed synchronous monolithic step-down switching regulator that consumes only 3 a of quiescent current. top and bottom power switches are included with all necessary circuitry to minimize the need for external components. the built-in current sense amplifier with monitor and control pins allows accurate input or output current regulation and limiting. low ripple burst mode operation enables high efficiency down to very low output currents while keeping the output ripple below 10mv p-p . a sync pin allows synchronization to an external clock. internal compensation with peak current mode topology allows the use of small inductors and results in fast transient response and good loop stability. the en/uv pin has an accurate 1 v threshold and can be used to program v in undervoltage lockout or to shut down the lt8613 reduc- ing the input supply current to 1 a. a capacitor on the tr/ss pin programs the output voltage ramp rate during start-up. the pg flag signals when v out is within 9% of the programmed output voltage as well as fault conditions. the lt 8613 is available in a small 28-lead 3mm 6mm qfn package with exposed pad for low thermal resistance. 5v step-down converter with 6a output current limit efficiency at 5v out a pplica t ions n rail-to-rail current sense amplifier with monitor n wide input voltage range: 3.4v to 42v n ultralow quiescent current burst mode ? operation: 3 a i q regulating 12v in to 3.3v out output ripple < 10mv p-p n high efficiency synchronous operation: 95% efficiency at 3a, 5v out from 12v in 94% efficiency at 3a, 3.3v out from 12v in n fast minimum switch-on time: 40ns n low dropout under all conditions: 250mv at 3a n allows use of small inductors n low emi n adjustable and synchronizable: 200khz to 2.2mhz n current mode operation n accurate 1v enable pin threshold n internal compensation n output soft-start and tracking n small thermally enhanced 3mm 6mm 28-lead qfn package n automotive and industrial supplies n general purpose step-down n cccv power supplies l, lt , lt c , lt m , burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. bst v in en/uv on off sync imon ictrl intv cc tr/ss rt sw lt8613 gnd pgnd isp bias isn pg 8613 ta01a fb 0.1f v out 5v 6a 1f 100f 10f v in 5.8v to 42v 10f 1f 10pf 3.9h 8m 1m 243k 60.4k f sw = 700khz l: epcos b82559 load current (a) 0 efficiency (%) 65 70 75 100 85 2 4 5 6 8613 ta01b 60 90 95 80 1 3 f sw = 700khz l = 3.9h v in = 24v v in = 12v lt8613 8613f
for more information www.linear.com/lt8613 2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , en / uv , pg , isp , isn ........................................... 42 v b ias .......................................................................... 25 v bs t pin above sw pin ................................................4v fb , tr / ss , rt, intv cc , imon , ictrl . ........................ 4 v sync voltage . ............................................................ 6 v operating junction temperature range ( note 2) lt 86 13 e ................................................. C4 0 to 125 c lt 86 13 i .................................................. C 40 to 125 c storage temperature range ...................... C 65 to 150 c (note 1) 11 top view 29 gnd ude package 28-lead (3mm 6mm) plastic qfn 12 13 14 28 27 26 25 6 5 4 3 2 1 sync tr/ss rt en/uv v in v in v in pgnd pgnd pgnd fb pg bias intv cc bst sw sw sw sw sw ictrl imon isn isp gnd gnd gnd gnd 7 19 20 21 22 23 24 18 8 9 10 17 16 15 v ja = 40c/w, v jc( pad ) = 5c/w exposed pad ( pin 29) is gnd, must be soldered to pcb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt8613eude#pbf lt8613eude#trpbf lghx 28-lead (3mm w 6mm) plastic qfn C40c to 125c lt8613iude#pbf lt8613iude#trpbf lghx 28-lead (3mm w 6mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ parameter conditions min typ max units minimum input voltage l 2.9 3.4 v v in quiescent current v en/uv = 0v, v sync = 0v l 1.0 1.0 5 20 a a v en/uv = 2v, not switching, v sync = 0v l 1.7 1.7 6 20 a a v en/uv = 2v, not switching, v sync = 2v 0.3 0.6 ma v in current in regulation v out = 0.97v, v in = 6v, output load = 100a v out = 0.97v, v in = 6v, output load = 1ma l l 24 230 60 370 a a feedback reference v oltage v in = 12v, i load = 500ma v in = 12v, i load = 500ma l 0.964 0.958 0.970 0.970 0.976 0.982 v v feedback v oltage line regulation v in = 4.0v to 25v, i load = 0.5a l 0.004 0.025 %/v feedback pin input current v fb = 1v C20 0.5 20 na bias pin current consumption v bias = 3.3v, i load = 2a, 2mhz 14 ma lt8613 8613f
for more information www.linear.com/lt8613 3 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt8613e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. the lt8613i is guaranteed over the full C40c to 125c operating junction the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. parameter conditions min typ max units minimum on-time i load = 2a, sync = 0v i load = 2a, sync = 3.3v l l 20 20 40 35 60 55 ns ns minimum off-t ime 50 85 120 ns oscillator frequency r t = 221k, i load = 1.5a r t = 60.4k, i load = 1.5a r t = 18.2k, i load = 1.5a l l l 180 665 1.85 210 700 2.00 240 735 2.15 khz khz mhz to p power nmos on-resistance i sw = 1a 65 m top power nmos current limit l 7.5 9.7 12.0 a bottom power nmos on-resistance v intvcc = 3.4v, i sw = 1a 29 m valley current limit v intvcc = 3.4v l 6 10 12 a sw leakage current v in = 42v, v sw = 0v, 42v C10 0.1 10 a en/uv pin threshold en/uv rising l 0.94 1.0 1.06 v en/uv pin hysteresis 40 mv en/uv pin current v en/uv = 2v C20 1 20 na pg upper threshold offset from v fb v fb falling l 6.5 9.0 11.5 % pg lower threshold offset from v fb v fb rising l C6.5 C9.0 C11.5 % pg hysteresis 1.3 % pg leakage v pg = 3.3v C40 40 na pg pull-down resistance v pg = 0.1v l 680 2000 sync threshold sync falling sync rising 0.7 1.0 1.0 1.3 1.4 1.55 v v sync pin current v sync = 2v C100 100 na tr/ss source current l 1.4 2.1 2.7 a tr/ss pull-down resistance fault condition, tr/ss = 0.1v 230 current sense voltage (v isp-isn ) v ictrl = 1.5v, v isn = 3.3v v ictrl = 1.5v, v isn = 0v v ictrl = 800mv, v isn = 3.3v v ictrl = 800mv, v isn = 0v v ictrl = 200mv, v isn = 3.3v v ictrl = 200mv, v isn = 0v l l l l l l 48 46 38 37 5 4 50 50.5 41 42 10 10.5 52 56 46 47 15 17 mv mv mv mv mv mv imon monitor pin v oltage v isp-isn = 50mv, v isn = 3.3v v isp-isn = 50mv, v isn = 0v v isp-isn = 10mv, v isn = 3.3v v isp-isn = 10mv, v isn = 0v l l l l 0.960 0.890 130 110 1.00 0.99 220 205 1.040 1.09 320 300 v v mv mv isp , isn pin bias current l C20 20 a temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 3: this ic includes overtemperature protection that is intended to protect the device during overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature will reduce lifetime. lt8613 8613f
for more information www.linear.com/lt8613 4 typical p er f or m ance c harac t eris t ics efficiency at 3.3v out efficiency vs frequency reference voltage en/uv pin thresholds load regulation line regulation efficiency at 5v out efficiency at 3.3v out efficiency at 5v out frequency (khz) 0 efficiency (%) 75 80 100 90 1000 1500 2000 2500 8613 g05 70 95 85 500 v out = 3.3v v in = 12v l = 3.9h load = 2a temperature (c) ?55 0.955 reference voltage (v) 0.958 0.964 0.967 0.970 0.985 0.976 5 65 95 125 8613 g06 0.961 0.979 0.982 0.973 ?25 35 155 temperature (c) ?55 0.95 en/uv threshold (v) 0.96 0.98 0.99 1.00 75 8613 g07 0.97 250 ?25 100 125 50 150 1.01 1.02 en/uv rising en/uv falling output load (a) 0 load regulation (%) ?0.4 ?0.3 ?0.1 ?0.2 0 0.5 0.2 2 4 5 6 8613 g08 ?0.5 0.3 0.4 0.1 1 3 load current (a) 0 efficiency (%) 65 70 75 100 85 2 4 5 6 8613 g01 60 90 95 80 1 3 f sw = 700khz l = 3.9h, epcos b82559 v in = 24v v in = 12v load current (a) 0 efficiency (%) 65 70 75 100 85 2 4 5 6 8613 g02 60 90 95 80 1 3 f sw = 700khz l = 3.9h, epcos b82559 v in = 24v v in = 12v load current (a) 0.00001 efficiency (%) 50 60 100 0.001 0.1 1 10 8613 g03 40 80 90 70 0.0001 0.01 f sw = 700khz l = 3.9h v in = 24v v in = 12v load current (a) 0.00001 efficiency (%) 50 60 100 0.001 0.1 1 10 8613 g04 40 80 90 70 0.0001 0.01 f sw = 700khz l = 3.9h v in = 24v v in = 12v input voltage (v) 0 change in v out (%) 0.02 0.06 0.10 40 8613 g09 ?0.02 ?0.06 0 0.04 0.08 ?0.04 ?0.08 ?0.10 10 20 30 50 v out = 5v load = 1a lt8613 8613f
for more information www.linear.com/lt8613 5 typical p er f or m ance c harac t eris t ics top fet current limit minimum on-time minimum off-time dropout voltage burst frequency switching frequency no load supply current top fet current limit vs duty cycle minimum load to full frequency (sync hi) input voltage (v) 0 input current (a) 2.0 2.4 2.6 2.8 3.8 3.2 10 20 8613 g10 2.2 3.4 3.6 3.0 30 40 50 v out = 5v duty cycle (%) 0 top fet current limit (a) 4 6 10 8 20 40 8613 g11 5 9 7 60 80 100 load current (ma) 0 switch frequency (khz) 0 500 600 800 8613 g17 400 300 200 100 700 100 200 500 300 400 v in = 12v v out = 5v l = 3.9h input voltage (v) 0 minimum load (ma) 0 40 50 60 8613 g18 30 20 10 10 20 50 30 40 temperature (c) ?50 current limit (a) 4 6 7 11 9 ?25 0 8613 g12 5 10 8 25 50 75 100 125 150 15% duty cycle 70% duty cycle load current (a) 0 minimum on-time (ns) 15 25 30 45 1 8613 g13 20 40 35 2 3 4 5 6 v sync = 0v v sync = 3.3v temperature (c) ?50 minimum off-time (ns) 60 80 85 100 ?25 8613 g14 75 70 65 95 90 0 25 50 75 150 100 125 load current (a) 0 dropout voltage (v) 0 0.3 0.4 0.6 8613 g15 0.2 0.1 0.5 1 2 3 6 4 5 temperature (c) ?50 switching frequency (khz) 660 710 720 740 8613 g16 700 690 680 670 730 ?25 0 25 50 150 10075 125 r t = 60.4k lt8613 8613f
for more information www.linear.com/lt8613 6 typical p er f or m ance c harac t eris t ics frequency foldback soft-start tracking soft-start current pg low thresholds pg high thresholds rt programmed switching frequency v in uvlo switching waveforms switching waveforms fb voltage (v) 0 switching frequency (khz) 300 400 500 0.6 1 8613 g19 200 100 0 0.2 0.4 0.8 600 700 800 v out = 3.3v v in = 12v v sync = 0v r t = 60.4k tr/ss voltage (v) 0 fb voltage (v) 0.8 1.0 1.2 0.6 1.0 8613 g20 0.6 0.4 0.2 0.4 0.8 1.2 1.4 0.2 0 temperature (c) ?50 ss pin current (a) 2.3 35 8613 g21 2.0 1.8 ?25 5 65 1.7 1.6 2.4 2.2 2.1 1.9 95 125 155 v ss = 0.5v temperature (c) ?55 7.0 pg threshold offset from v ref (%) 7.5 8.5 9.0 9.5 12.0 10.5 5 65 95 125 8613 g22 8.0 11.0 11.5 10.0 ?25 35 155 fb rising fb falling temperature (c) ?55 ?12.0 pg threshold offset from v ref (%) ?11.5 ?10.5 ?10.0 ?9.5 ?7.0 ?8.5 5 65 95 125 8613 g23 ?11.0 ?8.0 ?7.5 ?9.0 ?25 35 155 fb rising fb falling switching frequency (mhz) 0.2 rt pin resistor (k) 150 200 250 1.8 8613 g24 100 50 125 175 225 75 25 0 0.6 1 1.4 2.2 temperature (c) ?55 input voltage (v) 3.4 35 8613 g25 2.8 2.4 ?25 5 65 2.2 2.0 3.6 3.2 3.0 2.6 95 125 155 i l 1a/div v sw 5v/div 5s/div 12v in to 5v out at 20ma; front page app v sync = 0v 8613 g26 i l 1a/div v sw 5v/div 1s/div 12v in to 5v out at 2a front page app 8613 g27 lt8613 8613f
for more information www.linear.com/lt8613 7 typical p er f or m ance c harac t eris t ics switching waveforms transient response transient response transient response start-up dropout performance start-up dropout performance i l 1a/div v sw 10v/div 500ns/div 36v in to 5v out at 2a front page app 8613 g28 i load 1a/div v out 200mv/div 50s/div 0.1a to 1.1a transient 12v in to 5v out c out = 247f front page app 8613 g29 i load 1a/div v out 200mv/div 20s/div 1a to 2a transient 12v in to 5v out c out = 247f front page app 8613 g30 i load 1a/div v out 200mv/div 20s/div 1a to 3a transient 12v in to 5v out c out = 247f front page app 8613 g31 v in 2v/div v out 2v/div 100ms/div 2.5 load (2a in regulation) 8613 g32 v in v out v in 2v/div v out 2v/div 100ms/div 20 load (250ma in regulation) 8613 g33 v in v out lt8613 8613f
for more information www.linear.com/lt8613 8 typical p er f or m ance c harac t eris t ics v isp -v isn sense voltage imon voltage v isp -v isn sense voltage imon voltage ictrl voltage imon voltage ictrl voltage (mv) 0 0 max v isp -v isn voltage (mv) 10 20 30 40 50 60 500 1000 1500 2000 8613 g40 temperature (c) ?50 max v isp -v isn voltage (mv) 51 52 53 150 8613 g41 50 49 48 46 0 50 100 ?25 25 75 125 47 55 54 v isp = 0v v isp = 3v isp-isn common mode (v) 0 45 max v isp -v isn voltage (mv) 46 48 49 50 55 52 1 2 2.5 3 8613 g42 47 53 54 51 0.5 1.5 3.5 v isp -v isn (mv) 0 0 v imon (mv) 200 400 600 800 1000 1200 10 20 30 40 8613 g43 50 v sync = 3.3v v isp -v isn (mv) 0 0 v imon (mv) 200 400 600 800 1000 1200 10 20 30 40 8613 g44 50 v sync = 0v isp-isn common mode (v) 0 0.90 imon voltage (v) 0.95 1.00 1.05 1.10 0.5 1 1.5 2 8613 g45 2.5 3 3.5 v isp -v isn = 50mv lt8613 8613f
for more information www.linear.com/lt8613 9 p in func t ions sync (pin 1): external clock synchronization input. ground this pin for low ripple burst mode operation at low output loads. tie to a clock source for synchronization to an external frequency. apply a dc voltage of 3 v or higher or tie to intv cc for pulse-skipping mode. when in pulse- skipping mode, the i q will increase to several hundred a. when sync is dc high or synchronized, frequency foldback will be disabled. do not float this pin. tr/ss (pin 2): output tracking and soft-start pin. this pin allows user control of output voltage ramp rate during start-up. a tr/ss voltage below 0.97 v forces the lt8613 to regulate the fb pin to equal the tr/ss pin voltage. when tr/ss is above 0.97 v, the tracking function is disabled and the internal reference resumes control of the error amplifier. an internal 2.2 a pull-up current from intv cc on this pin allows a capacitor to program output voltage slew rate. this pin is pulled to ground with an internal 230 mosfet during shutdown and fault conditions; use a series resistor if driving from a low impedance output. this pin may be left floating if the tracking function is not needed. rt ( pin 3): a resistor is tied between rt and ground to set the switching frequency. en/uv (pin 4): the lt8613 is shut down when this pin is low and active when this pin is high. the hysteretic threshold voltage is 1.00 v going up and 0.96 v going down. tie to v in if the shutdown feature is not used. an external resistor divider from v in can be used to program a v in threshold below which the lt8613 will shut down. v in ( pins 5, 6, 7): the v in pins supply current to the lt8613 internal circuitry and to the internal topside power switch. these pins must be tied together and be locally bypassed. be sure to place the positive terminal of the input capaci - tor as close as possible to the v in pins, and the negative capacitor terminal as close as possible to the pgnd pins. pgnd (pins 8, 9, 10): power switch ground. these pins are the return path of the internal bottom- side power switch and must be tied together. place the negative terminal of the input capacitor as close to the pgnd pins as possible. gnd (pins 11, 12, 13, 14): it is recommended that these be connected to gnd so that the exposed pad gnd can be run to the top level gnd copper to enhance thermal performance. sw (pins 15C19): the sw pins are the outputs of the internal power switches. tie these pins together and con - nect them to the inductor and boost capacitor. this node should be kept small on the pcb for good per formance. bst (pin 20): this pin is used to provide a drive voltage, higher than the input voltage, to the topside power switch. place a 0.1 f boost capacitor as close as possible to the ic. intv cc (pin 21): internal 3.4 v regulator bypass pin. the internal power drivers and control circuits are pow- ered from this voltage. intv cc maximum output cur- rent is 20 ma. do not load the intv cc pin with external circuitry. intv cc current will be supplied from bias if v bias > 3.1 v, otherwise current will be drawn from v in . voltage on intv cc will vary between 2.8 v and 3.4 v when v bias is between 3.0 v and 3.6v . decouple this pin to power ground with at least a 1 f low esr ceramic capacitor placed close to the ic. bias ( pin 22): the internal regulator will draw current from bias instead of v in when bias is tied to a voltage higher than 3.1 v. for output voltages of 3.3 v and above this pin should be tied to v out . if this pin is tied to a supply other than v out use a 1f local bypass capacitor on this pin. pg (pin 23): the pg pin is the open-drain output of an internal comparator. pg remains low until the fb pin is within 9% of the final regulation voltage, and there are no fault conditions. pg is valid when v in is above 3.4v, regardless of en/uv pin state. fb (pin 24): the lt8613 regulates the fb pin to 0.970v. connect the feedback resistor divider tap to this pin. also, connect a phase lead capacitor between fb and v out . typically, this capacitor is 4.7pf to 10pf. isp (pin 25): current sense (+) pin. this is the noninvert - ing input to the current sense amplifier. lt8613 8613f
for more information www.linear.com/lt8613 10 b lock diagra m isn (pin 26): current sense (C) pin. this is the inverting input to the current sense amplifier. imon (pin 27): proportional-to-current monitor output. this pin sources a voltage 20 times the voltage between the isp and isn pins such that: v imon = 20 ? (v isp -v isn ). imon can source 200 a and sink 10 a. float imon if unused. ictrl (pin 28): current adjustment pin. ictrl adjusts the maximum isp-isn drop before the lt8613 reduces output current. connect directly to intv cc or float for full-scale isp-isn threshold of 50 mv or apply values between gnd and 1 v to modulate current limit. there is an internal 1.4 a pull-up current on this pin. float or tie to intv cc when unused. gnd ( exposed pad pin 29): ground. the exposed pad must be connected to the negative terminal of the input capacitor and soldered to the pcb in order to lower the thermal resistance. p in func t ions + + ? + ? slope comp internal 0.97v ref oscillator 200khz to 2.2mhz burst detect 3.4v reg m1 m2 c bst c f 8613 bd sw l bst switch logic and anti- shoot through error amp shdn 9% v c shdn tsd intv cc uvlo v in uvlo shdn tsd v in uvlo en/uv 1v + + ? + ? + ? isp r 20r v out r sen ictrl 1 isn 1.0v r imon gnd intv cc bias pgnd pg fb r1c1 r3 opt r4 opt r2 r t c ss (opt) v out tr/ss 2.1a rt sync v in v in c in c vcc 1.4a c out lt8613 8613f
for more information www.linear.com/lt8613 11 o pera t ion the lt8613 is a monolithic, constant frequency, current mode step-down dc/dc converter. an oscillator, with frequency set using a resistor on the rt pin, turns on the internal top power switch at the beginning of each clock cycle. current in the inductor then increases until the top switch current comparator trips and turns off the top power switch. the peak inductor current at which the top switch turns off is controlled by the voltage on the internal vc node. the error amplifier servos the vc node by comparing the voltage on the v fb pin with an internal 0.97v reference. when the load current increases it causes a reduction in the feedback voltage relative to the reference leading the error amplifier to raise the vc voltage until the average inductor current matches the new load current . when the top power switch turns off, the synchronous power switch turns on until the next clock cycle begins or inductor current falls to zero. if overload conditions result in more than 10 a flowing through the bottom switch ( valley current), the next clock cycle will be delayed until switch current returns to a safe level. the lt8613 includes a current control and monitoring loop using the isn, isp, imon and ictrl pins. the isp/ isn pins monitor the voltage across an external sense resistor such that the v isp -v isn does not exceed 50mv by limiting the peak inductor current controlled by the vc node. the current sense amplifier inputs ( isp/ isn) are rail- to-rail such that input, output, or other system currents may be monitored and regulated. the imon pin outputs a ground-referenced voltage equal to 20 times the voltage between the isp-isn pins for monitoring system currents. the ictrl pin can be used to override the internal 50mv limit between the isp, isn pin to a lower set point for the current control loop. if the en/uv pin is low, the lt8613 is shut down and draws 1 a from the input. when the en/uv pin is above 1v, the switching regulator will become active. to optimize efficiency at light loads, the lt8613 operates in burst mode operation in light load situations. between bursts, all circuitry associated with controlling the output switch is shut down, reducing the input supply current to 1.7a. in a typical application , 3 a will be consumed from the input supply when regulating with no load. the sync pin is tied low to use burst mode operation and can be tied to a logic high to use pulse-skipping mode. if a clock is applied to the sync pin the part will synchronize to an external clock frequency and operate in pulse-skipping mode. while in pulse-skipping mode the oscillator oper - ates continuously and positive sw transitions are aligned to the clock. during light loads, switch pulses are skipped to regulate the output and the quiescent current will be several hundred a. to improve efficiency across all loads, supply current to internal circuitry can be sourced from the bias pin when biased at 3.3v or above. else, the internal circuitry will draw current from v in . the bias pin should be connected to v out if the lt8613 output is programmed at 3.3 v or above. comparators monitoring the fb pin voltage will pull the pg pin low if the output voltage varies more than 9% ( typical) from the set point, or if a fault condition is present. the oscillator reduces the lt8613s operating frequency when the voltage at the fb pin is low. this frequency foldback helps to control the inductor current when the output voltage is lower than the programmed value which occurs during start-up or overcurrent conditions. when a clock is applied to the sync pin or the sync pin is held dc high, the frequency foldback is disabled and the switching frequency will slow down only during overcur - rent conditions. lt8613 8613f
for more information www.linear.com/lt8613 12 a pplica t ions i n f or m a t ion achieving ultralow quiescent current to enhance efficiency at light loads, the lt8613 operates in low ripple burst mode operation, which keeps the out - put capacitor charged to the desired output voltage while minimizing the input quiescent current and minimizing output voltage ripple. in burst mode operation the lt8613 delivers single small pulses of current to the output capaci - tor followed by sleep periods where the output power is supplied by the output capacitor. while in sleep mode the lt8613 consumes 1.7a. as the output load decreases, the frequency of single cur - rent pulses decreases ( see figure 1 a) and the percentage of time the lt8613 is in sleep mode increases, resulting in much higher light load efficiency than for typical convert- ers. by maximizing the time between pulses, the converter q uiescent current approaches 2.5 a for a typical application when there is no output load. therefore, to optimize the quiescent current performance at light loads, the current in the feedback resistor divider must be minimized as it appears to the output as load current. while in burst mode operation the current limit of the top switch is approximately 1 a resulting in output voltage ripple shown in figure 2. increasing the output capacitance will decrease the output ripple proportionally. as load ramps upward from zero the switching frequency will increase but only up to the switching frequency programmed by the resistor at the rt pin as shown in figure 1 a. the out - put load at which the lt8613 reaches the programmed frequency varies based on input voltage, output voltage, and inductor choice. for some applications it is desirable for the lt8613 to operate in pulse-skipping mode, offering two major differ - ences from burst mode operation. first is the clock stays awake at all times and all switching cycles are aligned to the clock. in this mode much of the internal circuitry is awake at all times, increasing quiescent current to several hundred a. second is that full switching frequency is reached at lower output load than in burst mode operation (see figure 1b). to enable pulse-skipping mode, the sync pin is tied high either to a logic output or to the intv cc pin. when a clock is applied to the sync pin the lt8613 will also operate in pulse-skipping mode. figure 1. sw frequency vs load information in burst mode operation (1a) and pulse-skipping mode (1b) figure 2. burst mode operation minimum load to full frequency (sync dc high) burst frequency (1a) (1b) load current (ma) 0 switch frequency (khz) 0 500 600 800 8613 f01a 400 300 200 100 700 100 200 500 300 400 v in = 12v v out = 5v l = 3.9h input voltage (v) 0 minimum load (ma) 0 40 50 60 8613 f01b 30 20 10 10 20 50 30 40 front page application i l 1a/div v sw 5v/div 5s/div 12v in to 5v out at 20ma; front page app v sync = 0v 8613 f02 lt8613 8613f
for more information www.linear.com/lt8613 13 a pplica t ions i n f or m a t ion fb resistor network the output voltage is programmed with a resistor divider between the output and the fb pin. choose the resistor values according to: r1 = r2 v out 0.970v C 1 ? ? ? ? ? ? (1) reference designators refer to the block diagram . 1% resistors are recommended to maintain output voltage accuracy. if low input quiescent current and good light - load efficiency are desired, use large resistor values for the fb resistor divider. the current flowing in the divider acts as a load current, and will increase the no-load input current to the converter, which is approximately: i q = 1.7a + v out r1 + r2 ? ? ? ? ? ? v out v in ? ? ? ? ? ? 1 n ? ? ? ? ? ? (2) where 1.7 a is the quiescent current of the lt8613 and the second term is the current in the feedback divider reflected to the input of the buck operating at its light load efficiency n. for a 3.3 v application with r1 = 1 m and r2 = 412 k, the feedback divider draws 2.3 a. with v in = 12v and n = 80%, this adds 0.8 a to the 1.7 a quiescent current resulting in 2.5 a no-load current from the 12v supply. note that this equation implies that the no-load current is a function of v in ; this is plotted in the typical performance characteristics section. when using large fb resistors, a 4.7 pf to 10 pf phase-lead capacitor should be connected from v out to fb. setting the switching frequency the lt8613 uses a constant frequency pwm architecture that can be programmed to switch from 200 khz to 2.2mhz by using a resistor tied from the rt pin to ground. a table showing the necessary r t value for a desired switching frequency is in table 1. the r t resistor required for a desired switching frequency can be calculated using: r t = 46.5 f sw C 5.2 (3) where r t is in k and f sw is the desired switching fre- quency in mhz. table 1. sw frequency vs r t value f sw (mhz) r t (k) 0.2 232 0.3 150 0.4 110 0.5 88.7 0.6 71.5 0.7 60.4 0.8 52.3 1.0 41.2 1.2 33.2 14 28.0 1.6 23.7 1.8 20.5 2.0 18.2 2.2 15.8 operating frequency selection and trade-offs selection of the operating frequency is a trade-off between efficiency, component size, and input voltage range. the advantage of high frequency operation is that smaller induc - tor and capacitor values may be used. the disadvantages are lower efficiency and a smaller input voltage range. the highest switching frequency (f sw(max) ) for a given application can be calculated as follows: f sw(max) = v out + v sw(bot) t on(min) v in C v sw(top) + v sw(bot) ( ) (4) where v in is the typical input voltage, v out is the output voltage, v sw(top) and v sw(bot) are the internal switch drops (~0.4v, ~0.18 v, respectively at maximum load) and t on(min) is the minimum top switch on-time ( see the electrical characteristics). this equation shows that a slower switching frequency is necessary to accommodate a high v in /v out ratio. for transient operation, v in may go as high as the abso- lute maximum rating of 42 v regardless of the r t value, however the lt8613 will reduce switching frequency as necessary to maintain control of inductor current to as - sure safe operation. lt8613 8613f
for more information www.linear.com/lt8613 14 a pplica t ions i n f or m a t ion the lt8613 is capable of a maximum duty cycle of greater than 99%, and the v in -to-v out dropout is limited by the r ds(on) of the top switch. in this mode the lt8613 skips switch cycles, resulting in a lower switching frequency than programmed by rt . for applications that cannot allow deviation from the pro - grammed switching frequency at low v in /v out ratios use the following formula to set switching frequency: v in(min) = v out + v sw(bot) 1C f sw ? t off(min) C v sw(bot) + v sw(top) (5) where v in(min) is the minimum input voltage without skipped cycles, v out is the output voltage, v sw(top) and v sw(bot) are the internal switch drops (~0.4v, ~0.18v, respectively at maximum load), f sw is the switching fre- quency ( set by rt ), and t off(min) is the minimum switch off- time. note that higher switching frequency will increase the minimum input voltage below which cycles will be dropped to achieve higher duty cycle. inductor selection and maximum output current the lt8613 is designed to minimize solution size by allowing the inductor to be chosen based on the output load requirements of the application. during overload or short-circuit conditions the lt8613 safely tolerates opera - tion with a saturated inductor through the use of a high speed peak-current mode ar chitecture. a good first choice for the inductor value is: l = v out + v sw(bot) f sw (6) where f sw is the switching frequency in mhz, v out is the output voltage, v sw(bot) is the bottom switch drop (~0.18v) and l is the inductor value in h. to avoid overheating and poor efficiency, an inductor must be chosen with an rms current rating that is greater than the maximum expected output load of the application. in addition, the saturation current ( typically labeled i sat ) rating of the inductor must be higher than the load current plus 1/2 of in inductor ripple current: i l(peak) = i load(max) + 1 2 ? i l (7) where ? i l is the inductor ripple current as calculated in equation 9 and i load(max) is the maximum output load for a given application. as a quick example, an application requiring 4 a output should use an inductor with an rms rating of greater than 4a and an i sat of greater than 5 a. during long duration overload or short-circuit conditons, the inductor rms is greater to avoid overheating of the inductor. to keep the efficiency high, the series resistance ( dcr) should be less than 0.020, and the core material should be intended for high frequency applications. the lt8613 limits the peak switch current in order to protect the switches and the system from overload faults. the top switch current limit (i lim ) is at least 7.5 a at low duty cycles and decreases linearly to 6 a at dc = 0.8. the inductor value must then be sufficient to supply the desired maximum output current (i out(max) ), which is a function of the switch current limit (i lim ) and the ripple current. i out(max) = i lim C ? i l 2 (8) the peak-to-peak ripple current in the inductor can be calculated as follows: ? i l = v out l ? f sw ? 1C v out v in(max) ? ? ? ? ? ? ? ? (9) where f sw is the switching frequency of the lt8613, and l is the value of the inductor. therefore, the maximum output current that the lt8613 will deliver depends on the switch current limit, the inductor value, and the input and output voltages. the inductor value may have to be increased if the inductor ripple current does not allow sufficient maximum output current (i out(max) ) given the switching frequency, and maximum input voltage used in the desired application. the optimum inductor for a given application may differ from the one indicated by this design guide. a larger value inductor provides a higher maximum load current and reduces the output voltage ripple. for applications requir - ing smaller load currents, the value of the inductor may be lower and the lt8613 may operate with higher ripple lt8613 8613f
for more information www.linear.com/lt8613 15 a pplica t ions i n f or m a t ion current. this allows use of a physically smaller inductor, or one with a lower dcr resulting in higher efficiency. be aware that low inductance may result in discontinuous mode operation, which further reduces maximum load current. for more information about maximum output current and discontinuous operation, see linear technologys application note 44. finally, for duty cycles greater than 50% (v out /v in > 0.5), a minimum inductance is required to avoid sub-harmonic oscillation. see application note 19. input capacitor bypass the input of the lt8613 circuit with a ceramic ca - pacitor of x7r or x5r type placed as close as possible to the v in and pgnd pins. y5v types have poor performance over temperature and applied voltage, and should not be used. a 10 f ceramic capacitor is adequate to bypass the lt8613 and will easily handle the ripple current. note that larger input capacitance is required when a lower switching frequency is used. if the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. this can be provided with a low performance electrolytic capacitor. step-down regulators draw current from the input sup - ply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt8613 and to force this very high frequency switching current into a tight local loop, minimizing emi. a 10 f capacitor is capable of this task, but only if it is placed close to the lt8613 ( see the pcb layout section). a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the lt8613. a ceramic input capacitor combined with trace or cable inductance forms a high quality ( under damped) tank cir - cuit. if the lt8613 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the lt8613s voltage rating. this situation is easily avoided ( see linear technology application note 88). output capacitor and output ripple the output capacitor has two essential functions. along with the inductor, it filters the square wave generated by the lt8613 to produce the dc output. in this role it determines the output ripple, thus low impedance at the switching frequency is important. the second function is to store energy in order to satisfy transient loads and stabilize the lt8613s control loop. ceramic capacitors have very low equivalent series resistance ( esr) and provide the best ripple performance. for good starting values, see the typical applications section. use x5r or x7r types. this choice will provide low output ripple and good transient response. transient performance can be improved with a higher value output capacitor and the addition of a feedforward capacitor placed between v out and fb. increasing the output capacitance will also decrease the output voltage ripple. a lower value of output capacitor can be used to save space and cost but transient performance will suffer and may cause loop instability. see the typical applications in this data sheet for suggested capacitor values. when choosing a capacitor, special attention should be given to the data sheet to calculate the effective capacitance under the relevant operating conditions of voltage bias and temperature. a physically larger capacitor or one with a higher voltage rating may be required. lt8613 8613f
for more information www.linear.com/lt8613 16 a pplica t ions i n f or m a t ion enable pin the lt8613 is in shutdown when the en pin is low and active when the pin is high. the rising threshold of the en comparator is 1.0 v, with 40 mv of hysteresis. the en pin can be tied to v in if the shutdown feature is not used, or tied to a logic level if shutdown control is required. adding a resistor divider from v in to en programs the lt8613 to regulate the output only when v in is above a desired voltage ( see the block diagram). typically, this threshold, v in(en) , is used in situations where the input supply is current limited, or has a relatively high source resistance. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. the v in(en) threshold prevents the regulator from operating at source voltages where the problems might occur. this threshold can be adjusted by setting the values r3 and r4 such that they satisfy the following equation: v in(en) = r3 r4 + 1 ? ? ? ? ? ? ? 1.0v (10) where the lt8613 will remain off until v in is above v in(en) . due to the comparators hysteresis, switching will not stop until the input falls slightly below v in(en) . when operating in burst mode operation for light load currents, the current through the v in(en) resistor network can easily be greater than the supply current consumed by the lt8613. therefore, the v in(en) resistors should be large to minimize their effect on efficiency at low loads. current control loop in addition to regulating the output voltage the lt8613 includes a current regulation loop for setting the average input or output current limit as shown in the typical ap - plications section. the lt8613 measures voltage drop across an external current sense resistor using the isp and isn pins. this resistor may be connected between the inductor and the output capacitor to sense the output current or may be placed between the v in bypass capacitor and the input power source to sense input current. the current loop modulates the internal cycle-by-cycle switch current limit such that the average voltage across isp-isn pins does not exceed 50mv. care must be taken and filters should be used to assure the signal applied to the isn and isp pins has a peak-to- peak ripple of less than 30 mv for accurate operation. in addition to high crest factor current waveforms such as the input current of dc/dc regulators, another cause of high ripple voltage across the sense resistor is excessive resistor esl. typically the problem is solved by using a small ceramic capacitor across the sense resistor or using a filter network between the isp and isn pins. the ictrl pin allows the isp-isn set point to be linearly controlled from 50 mv to 0 mv as the ictrl pin is ramped from 1 v down to 0 v, respectively and as shown in figure?3. when this functionality is unused the ictrl pin may be tied to intv cc or floated. in addition the ictrl pin includes a 2 a pull-up source such that a capacitor may be added for soft-start functionality. the imon pin is a voltage output proportional to the voltage across the current sense resistor such that v imon = 20 ? (isp-isn) as shown in figure 4. this output can be used to monitor the input or output current of the lt 8613 or may be an input to an adc for further processing. figure 3. lt8613 sense voltage vs ictrl voltage ictrl voltage (mv) 0 0 max v isp -v isn voltage (mv) 10 20 30 40 50 60 500 1000 1500 2000 8613 f03 lt8613 8613f
for more information www.linear.com/lt8613 17 a pplica t ions i n f or m a t ion capacitor on tr/ss enables soft starting the output to pre- vent current surge on the input supply. during the soft- start ramp the output voltage will proportionally track the tr/ ss pin voltage. for output tracking applications, tr / ss can be externally driven by another voltage source. from 0 v to 0.97v, the tr/ss voltage will override the internal 0.97v reference input to the error amplifier, thus regulating the fb pin voltage to that of tr/ss pin. when tr/ss is above 0.97v , tracking is disabled and the feedback voltage will regulate to the internal reference voltage. the tr / ss pin may be left floating if the function is not needed. an active pull-down circuit is connected to the tr/ss pin which will discharge the external soft-start capacitor in the case of fault conditions and restart the ramp when the faults are cleared. fault conditions that clear the soft-start capacitor are the en/uv pin transitioning low, v in voltage falling too low, or thermal shutdown. output power good when the lt8613s output voltage is within the 9% window of the regulation point, which is a v fb voltage in the range of 0.883 v to 1.057 v ( typical), the output voltage is considered good and the open-drain pg pin goes high impedance and is typically pulled high with an external resistor. otherwise, the internal pull-down device will pull the pg pin low. to prevent glitching both the upper and lower thresholds include 1.3% of hysteresis. the pg pin is also actively pulled low during several fault conditions: en/uv pin is below 1 v, intv cc has fallen too low, v in is too low, or thermal shutdown. synchronization to select low ripple burst mode operation, tie the sync pin below 0.4v ( this can be ground or a logic low output). to synchronize the lt8613 oscillator to an external frequency connect a square wave (with 20% to 80% duty cycle) to the sync pin. the square wave amplitude should have val - leys that are below 0.4 v and peaks above 2.4v ( up to 6v). figure 4. lt8613 sense voltage vs imon voltage intv cc regulator an internal low dropout ( ldo) regulator produces the 3.4 v supply from v in that powers the drivers and the internal bias circuitry. the intv cc can supply enough current for the lt8613s circuitry and must be bypassed to ground with a minimum of 1 f ceramic capacitor . good bypassing is necessary to supply the high transient currents required by the power mosfet gate drivers. to improve efficiency the internal ldo can also draw current from the bias pin when the bias pin is at 3.1 v or higher. typically the bias pin can be tied to the output of the lt8613, or can be tied to an external supply of 3.3 v or above. if bias is connected to a supply other than v out , be sure to bypass with a local ceramic capacitor. if the bias pin is below 3.0v, the internal ldo will consume current from v in . applications with high input voltage and high switching frequency where the internal ldo pulls current from v in will increase die temperature because of the higher power dissipation across the ldo. do not connect an external load to the intv cc pin. output voltage tracking and soft-start t he lt8613 allows the user to program its output voltage ramp rate by means of the tr/ ss pin. an internal 2.2a pulls up the tr/ ss pin to intv cc . putting an external v isp -v isn (mv) 0 0 v imon (mv) 200 400 600 800 1000 1200 10 20 30 40 8613 f04 50 v sync = 3.3v lt8613 8613f
for more information www.linear.com/lt8613 18 a pplica t ions i n f or m a t ion figure 5. reverse v in protection the lt8613 will not enter burst mode operation at low output loads while synchronized to an external clock, but instead will pulse skip to maintain regulation. the lt8613 may be synchronized over a 200 khz to 2.2 mhz range. the r t resistor should be chosen to set the lt8613 switching frequency equal to or below the lowest synchronization input. for example, if the synchronization signal will be 500khz and higher, the r t should be selected for 500khz. the slope compensation is set by the r t value, while the minimum slope compensation required to avoid subhar- monic oscillations is established by the inductor size, input voltage, and output voltage. since the synchroniza- tion frequency will not change the slopes of the inductor current waveform, if the inductor is large enough to avoid subharmonic oscillations at the frequency set by r t , then the slope compensation will be sufficient for all synchro- nization frequencies. for some applications it is desirable for the lt8613 to operate in pulse-skipping mode, offering two major differ - ences from burst mode operation. first is the clock stays awake at all times and all switching cycles are aligned to the clock. second is that full switching frequency is reached at lower output load than in burst mode operation. these two differences come at the expense of increased quiescent current. to enable pulse-skipping mode, the sync pin is tied high either to a logic output or to the intvcc pin. the lt8613 does not operate in forced continuous mode regardless of sync signal. never leave the sync pin floating. shorted and reversed input protection the lt8613 will tolerate a shorted output. several features are used for protection during output short-circuit and brownout conditions. the first is the switching frequency will be folded back while the output is lower than the set point to maintain inductor current control. second, the bottom switch current is monitored such that if inductor current is beyond safe levels switching of the top switch will be delayed until such time as the inductor current falls to safe levels. frequency foldback behavior depends on the state of the sync pin: if the sync pin is low the switching frequency will slow while the output voltage is lower than the pro - grammed level. if the sync pin is connected to a clock source or tied high, the lt86 13 w ill stay at the programmed frequency without foldback and only slow switching if the inductor current exceeds safe levels. there is another situation to consider in systems where the output will be held high when the input to the lt8613 is absent. this may occur in battery charging applications or in battery-backup systems where a battery or some other supply is diode ored with the lt8613s output. if the v in pin is allowed to float and the en pin is held high (either by a logic signal or because it is tied to v in ), then the lt8613 s internal circuitry will pull its quiescent current through its sw pin. this is acceptable if the system can tolerate several a in this state. if the en pin is grounded the sw pin current will drop to near 1 a. however, if the v in pin is grounded while the output is held high, regard- less of en, parasitic body diodes inside the lt8613 can pull current from the output through the sw pin and the v in pin. figure 5 shows a connection of the v in and en/uv pins that will allow the lt8613 to run only when the input voltage is present and that protects against a shorted or reversed input. v in v in d1 lt8613 en/uv 8613 f05 gnd lt8613 8613f
for more information www.linear.com/lt8613 19 a pplica t ions i n f or m a t ion figure 6. recommended pcb layout for the lt8613 pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. figure 6 shows the recommended component placement with trace, ground plane and via locations. note that large, switched currents flow in the lt8613s v in pins, pgnd pins, and the input ca- pacitor (c 1). the loop formed by the input capacitor should be as small as possible by placing the capacitor adjacent to the v in and pgnd pins. when using a physically large input capacitor the resulting loop may become too large in which case using a small case/ value capacitor placed close to the v in and pgnd pins plus a larger capacitor further away is preferred. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer. the sw and boost nodes should be as small as possible. finally, keep the fb and rt nodes small so that the ground traces will shield them from the sw and boost nodes. the exposed pad on the bottom of the package must be soldered to ground so that the pad is connected to ground electrically and also acts as a heat sink thermally. to keep thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the lt8613 to additional ground planes within the circuit board and on the bottom side. high temperature considerations for higher ambient temperatures, care should be taken in the layout of the pcb to ensure good heat sinking of the lt8613. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to large copper layers below with thermal vias; these layers will spread heat dissipated by the lt8613. placing additional vias can reduce thermal resistance further. the maximum load current should be derated as the ambient temperature approaches the maximum junction rating. power dissipation within the lt8613 can be estimated by calculating the total power loss from an efficiency measurement and subtracting the inductor loss. the die temperature is calculated by multiplying the lt8613 power dissipation by the thermal resistance from junction to ambient. the lt 8613 will stop switching and indicate a fault condition if safe junction temperature is exceeded. v out 8613 f06 outline of local ground plane sw bst bias intv cc gnd 17 16 15 18 19 20 21 22 23 pg fb gnd v out 24 sync tr/ss rt en/uv v in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 imon isn isp ictrl v out line to bias v out line to isn line to isp vias to ground plane lt8613 8613f
for more information www.linear.com/lt8613 20 typical a pplica t ions 5v step-down with 5a output current limit 3.3v step-down with 1a input current limit and 7v v in undervoltage lockout 3.3v step-down with 1a input current limit bst v in en/uv on off sync imon ictrl intv cc tr/ss rt sw lt8613 gnd pgnd isp isn bias pg 8613 ta02 fb 0.1f v out 5v 5a 1f 100f 10f v in 5.8v to 42v 1f 10pf 3.3h 0.010 1m 243k 52.3k f sw = 800khz l: vishay ihlp2525ez-01 bst v in en/uv on off sync imon ictrl intv cc tr/ss rt sw lt8613 isn isp pgnd gnd pg bias 8613 ta03 fb 0.10f v out 3.3v 100f 10f 1f v in 4.1v to 42v 1f 3.3h 1m 0.050 412k 41.2k f sw = 1mhz 4.7pf l: vishay ihlp2525ez-01 bst v in en/uv sync imon ictrl intv cc tr/ss rt sw lt8613 isn isp pgnd gnd pg bias 8613 ta04 fb 0.1f v out 3.3v 100f 10f 604k 100k 1f v in 4.1v to 42v 1f 3.3h 1m 0.050 412k 60.4k f sw = 700khz l: vishay ihlp2525ez-01 4.7pf lt8613 8613f
for more information www.linear.com/lt8613 21 typical a pplica t ions digitally controlled current/voltage source cccv battery charger C3.3v negative converter with 2a output current limit bst v in en/uv on off sync imon ictrl adc c dac intv cc tr/ss rt sw lt8613 gnd isp bias isn pg 8613 ta05 fb 0.1f v out 3.3v 6a 1f 4.7pf 100f 10h v in 4.1v to 42v 1f 3.3h 0.008 1m 412k 60.4k f sw = 700khz pgnd l: vishay ihlp2525ez-01 bst v in en/uv on off sync imon ictrl intv cc tr/ss rt sw lt8613 gnd isp isn bias pg 8613 ta06 fb 0.1f v out 4.1v 5a 1f 10pf li-ion battery 47f 10h d1 v in 5v to 42v 1f 3.3h 0.010 324k 100k 60.4k f sw = 700khz pgnd + l: vishay ihlp2525ez-01 bst v in en/uv sync imon 60.4k 0.1f ictrl intv cc tr/ss rt sw lt8613 gnd isp isn bias pg 8613 ta07 fb 0.1f 1f v out ?3.3v 2a 10pf 47f 4.7f v in 3.8v to 38v 1f 4.7h 1m 0.025 412k 60.4k f = 700khz l: coilcraft xal6060 pgnd 10f lt8613 8613f
for more information www.linear.com/lt8613 22 2mhz, 3.3v step-down with power good without current sense 1v step-down with 5a output current limit 12v step-down with 5a output current limit typical a pplica t ions bst v in en/uv sync imon ictrl intv cc tr/ss rt sw lt8613 gnd isp isn bias pg 8613 ta08 fb 0.1f v out 3.3v 6a pgood 4.7pf 100f v in 4.1v to 42v 1f 1h 1m 412k 150k 18.2k f = 2mhz l: vishay ihlp2525cz-01 pgnd 10f on off bst v in en/uv sync imon ictrl intv cc tr/ss rt sw lt8613 gnd isp isn bias pg 8613 ta09 fb 0.1f v out 0.97v 5a 2100f v in 3.8v to 42v 1f 1h 0.010 150k f = 300khz l: vishay ihlp2525cz-01 pgnd 10f on off 1f bst v in en/uv sync imon ictrl intv cc tr/ss rt sw lt8613 gnd isp isn bias pg 8613 ta10 fb 0.1f v out 12v 5a 22f v in 13v to 42v 1f 10h 0.010 60.4k f = 700khz l: coilcraft xal6060 pgnd 10f on off 1f 1m 10pf 88.7k lt8613 8613f
for more information www.linear.com/lt8613 23 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. typical a pplica t ions note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 4.50 ref 5.10 0.05 6.50 0.05 1.50 ref 2.10 0.05 3.50 0.05 package outline 1.70 0.05 0.50 bsc 4.75 0.05 3.00 0.10 1.50 ref 6.00 0.10 pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 4.50 ref 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ude28) qfn 0612 rev ? r = 0.05 typ 1.70 0.10 4.75 0.10 ude package 28-lead plastic qfn (3mm 6mm) (reference ltc dwg # 05-08-1926 rev ?) 5a led driver bst v in en/uv sync imon ictrl intv cc tr/ss rt sw lt8613 gnd isp isn bias pg 8613 ta11 fb 0.1f 5a 10f v in 3.8v to 42v 1f 4.7h 0.010 60.4k f = 700khz l: coilcraft xal6060 pgnd 4.7f on off 1f d1 420k 10pf 100k lt8613 8613f
for more information www.linear.com/lt8613 24 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2012 lt 1114 ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt8613 r ela t e d p ar t s typical a pplica t ion coincident tracking step-downs each with 5a output current limit part number description comments lt8610a/ lt8610ab 42v, 3.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q? =?2.5a v in ?=?3.4v?to?42v, v out(min) ?=?0.97v, i q ?=?2.5a, i sd ?

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